1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to an alignment mark used for superimpose the first electrode on an element active region with high accuracy in a semiconductor device with trench isolation structure.
2. Description of the Background Art
FIGS. 45 to 51 are cross sections showing steps for manufacturing a semiconductor device with trench isolation structure in the background art. The manufacturing method will be discussed below, with reference to these figures.
First, a silicon oxide film 3 and a silicon nitride film 4 are formed on a silicon substrate 1 in this order. With a field mask, the silicon oxide film 3 and the silicon nitride film 4 are patterned. The resist used for the patterning is removed and a dry etching of 2000 to 4000 xc3x85 is performed to form trenches 10 (10A to 10C) having a predetermined depth in the silicon substrate 1 as shown in FIG. 45. Specifically, relatively wide trenches 10A are formed in an alignment mark area 11A, narrow trenches 10B are formed in a memory cell area 11B and wide trenches 10C are formed in a peripheral circuit area 11C. Thus, the trenches 10A and 10C in the alignment mark area 11A and the peripheral circuit area 11C are formed in a loose pattern and the trenches 10B in the memory cell 11B are formed in a dense pattern.
Subsequently, as shown in FIG. 46, side surfaces and bottom surfaces of the trenches 10A to 10C are oxidized by thermal oxidation and then a silicon oxide film 2 is deposited by CVD. While the silicon oxide film 2 on the wide trenches 10A and 10C is as thick as the deposited film, the silicon oxide film 2 on the narrow trench 10B is thicker than the deposited film since the insulating film is buried into the narrow trenches at an early stage of deposition. In other words, there is a difference in thickness between the silicon oxide film 2 on the trenches 10B and that on the trenches 10A and 10C. The difference is referred to as a thickness difference of silicon oxide film on trench.
In order to reduce the thickness difference of silicon oxide film on trench, a resist pattern 5 is formed only on the buried silicon oxide films 2 on the wide trenches 10A and 10C with a mask which is different from the field mask, as shown in FIG. 47, and then a dry etching is performed to remove part of the silicon oxide film which is convex. Hereinafter, this step is referred to as preetching in some cases.
After removing the resist pattern 5, the whole surface is entirely polished by CMP (Chemical Mechanical Polishing), as shown in FIG. 48, to remove the silicon oxide film on the silicon nitride film 4 and part of the silicon oxide film on the trenches 10A to 10C.
Next, as shown in FIG. 49, the silicon nitride film 4 is removed with phosphoric acid and the silicon oxide film 3 is removed with hydrofluoric acid, to form a buried silicon film 2A in the alignment mark area 11A, a buried silicon film 2B in the memory cell area 11B and a buried silicon film 2C in the peripheral circuit area 11C which constitute a trench isolation structure.
Subsequently, as shown in FIG. 50, a gate oxide film 6 is formed by thermal oxidation and a polysilicon film 7 doped with phosphorus and a tungsten silicide film 8 are formed on the gate oxide film 6 in this order.
Next, as shown in FIG. 51, with the buried silicon oxide film 2A (alignment mark) which is formed on the step of forming the isolation structure in the alignment mark area 11A, a pattern for superimposing a gate electrode on an isolation region is formed by photolithography, and gate electrodes 14 are formed in the memory cell area 11B and the peripheral circuit area 11C through partially removing part of the tungsten silicide film 8 and the polysilicon film 7 by dry etching.
The semiconductor device and the method for manufacturing the same in the background art as discussed above have the following problem.
In patterning of the gate electrode 14 made of the first electrode material, to form a pattern in a predetermined portion of the active region, it is necessary to superimpose it on the active region. For this superimposition, the alignment mark 2A which is formed in the step of forming the isolation structure in the alignment mark area 11A is used.
In the semiconductor device with trench isolation structure, however, it is difficult to detect the mark by the height difference of surface since there is little difference in height of the alignment mark. Moreover, since a silicide film which is part of the gate electrode material reflects light (monochromatic light (wavelength: 633 m)) and white light (wavelength: 530 to 800 m), not passing light, it is also difficult to detect the mark by image recognition.
With difficulties of the mark detection, the accuracy of alignment becomes lower and therefore it disadvantageously becomes impossible to achieve accurate superimposition of gate masks for formation of gate electrode.
The present invention is directed to a semiconductor device in which semiconductor elements are isolated with a trench isolation structure. According to a first aspect of the present invention, the semiconductor device comprises:
a semiconductor substrate;
an alignment mark area provided on the semiconductor substrate, having a first trench in an upper portion of the semiconductor substrate and an alignment insulating film provided in the first trench;
and an element formation area provided on the semiconductor substrate, having an isolation insulating film used for isolating a plurality of semiconductor elements, the isolation insulating film filling a second trench provided in the upper portion of the semiconductor substrate.
In the semiconductor device of the first aspect, the alignment insulating film has a height difference with the highest portion of the alignment insulating film being higher than a surface of the semiconductor substrate and a surface of the lowest portion being lower than the surface of the semiconductor substrate.
According to a second aspect of the present invention, the semiconductor device comprises:
a semiconductor substrate; an alignment mark area provided on the semiconductor substrate, having a first trench in an upper portion of the semiconductor substrate and an alignment insulating film provided in the first trench, the alignment insulating film being formed in a peripheral portion other than a center portion of the first trench;
and an element formation area provided on the semiconductor substrate, having an isolation insulating film used for isolating a plurality of semiconductor elements, the isolation insulating film filling a second trench provided in the upper portion of the semiconductor substrate, a bottom surface of the center portion of the first trench being formed deeper than the a bottom surface of the second trench. In the semiconductor device of the second aspect, the alignment insulating film has a height difference between the highest portion and the bottom surface of the center portion.
According to a third aspect of the present invention, in the semiconductor device, the semiconductor substrate includes an SOI substrate having an underlying substrate, a buried insulating film formed on the underlying substrate and an SOI layer formed on the buried insulating film, and the first and second trenches penetrate the SOI layer and the center portion of the first trench is formed by further removing a part of the buried insulating film.
According to a fourth aspect of the present invention, the semiconductor device further comprises:
a control electrode provided on the element formation area, for controlling a device operation;
an interlayer insulating film provided on the semiconductor substrate including the control electrode and a portion above the first trench;
a first through hole penetrating the interlayer insulating film, the center portion of the first trench and the buried insulating film to reach the underlying substrate;
a second through hole penetrating the interlayer insulating film to reach the control electrode;
and an interconnection layer electrically connected to the control electrode through the second through hole.
According to a fifth aspect of the present invention, the semiconductor device further comprises an element-on-underlying-substrate formation area being the underlying substrate in which semiconductor elements are formed.
The present invention is also directed to a method for manufacturing a semiconductor device with trench isolation structure. According to a sixth aspect of the present invention, the method comprises the steps of:
(a) preparing a semiconductor substrate having an alignment mark area and an element formation area;
(b) forming first and second trenches at one time in upper portions of the alignment mark area and the element formation area of the semiconductor substrate, respectively, the first and second trenches having almost the same depth at their bottom surfaces from a surface of the semiconductor substrate;
(c) forming an insulating film entirely on the surface of the semiconductor substrate;
(d) forming a resist pattern at least on the insulating film corresponding to the peripheral vicinity region external to the first trench in the alignment mark area;
(e) removing the insulating film with the resist pattern used as a mask;
(f) further removing the insulating film after removing the resist pattern, the step (f) being performed so as to leave a part of the insulating film in the first trench and the insulating film which is buried in the second trench, the first trench after the step (f) being defined as an alignment mark;
(g) forming an electrode layer entirely on the semiconductor substrate; and
(h) recognizing a position of the alignment mark to pattern the electrode layer on the element formation area.
In the method of the sixth aspect, the alignment mark has a height difference between a center portion of the first trench and a peripheral portion other than the center portion.
According to a seventh aspect of the present invention, in the method, the resist pattern is further formed on the insulating film corresponding to the first trench in the alignment mark area in the step (d), and the alignment mark includes an alignment insulating film which is the insulating film left in the first trench after the step (f), the alignment insulating film being formed so that the highest portion of the alignment insulating film formed on the peripheral portion becomes higher than the surface of the semiconductor substrate and a surface of the alignment insulating film formed on the center portion becomes lower than the surface of the semiconductor substrate to have a height difference.
According to an eighth aspect of the present invention, in the method, the resist pattern is formed only on the insulating film corresponding to the peripheral vicinity region of the first trench in the alignment mark area in the step (d), the step (f) includes the step of removing the insulting film on the center portion of the first trench while leaving the insulating film on the peripheral portion of the first trench as the alignment insulating film and removing a part of the semiconductor substrate beneath the center portion of the first trench, the part of the semiconductor substrate which is removed being defined as the deepest portion of the first trench, and the alignment mark includes the alignment insulating film and the first trench, and has a height difference between the highest portion of the alignment insulating film and a bottom surface of the deepest portion of the first trench.
According to a ninth aspect of the present invention, in the method, the semiconductor substrate includes an underlying substrate, a buried insulating film formed on the underlying substrate, and an SOI layer formed on the buried insulating film, the step (b) includes the step of forming the first and second trenches so as to penetrate the SOI layer, and the part of the semiconductor substrate which is removed in the step (f) includes a part of the buried insulating film.
According to a tenth aspect of the present invention, in the method, the electrode layer patterned in the step (h) is formed on the element formation area and includes a control electrode for controlling a device operation, and the method further comprises the steps of:
(i) entirely forming an interlayer insulating film;
(j) forming first and second through holes on the interlayer insulating film formed on the center portion of the first trench and the control electrode, respectively, the first through hole being formed so as to further penetrate the buried insulating film to reach the underlying substrate;
(k) forming a metal layer on the interlayer insulating film including the first and second through holds; and
(l) patterning the metal layer to form an interconnection layer.
According to an eleventh aspect of the present invention, in the method, the semiconductor substrate further includes a circuit-on-underlying-substrate area, the step (b) includes the step of forming a third trench penetrating the SOI layer and being wider than each of the first and second trenches, no resist pattern is formed on the third trench in the step (d), and the step (f) includes the step of removing all the insulating film on the third trench and the buried insulating film beneath the third trench to expose the underlying substrate.
According to a twelfth aspect of the present invention, in the method, the second trench includes a first circuit trench being relatively narrow and a second circuit trench being relatively wider, the element formation area includes a first circuit formation area isolated by the first circuit trench and a second circuit formation area isolated by the second circuit trench, and no resist pattern is formed on the insulating film corresponding to the first circuit formation area and the resist pattern is formed on the insulating film corresponding to the second circuit formation area in the step (d).
According to a thirteenth aspect of the present invention, in the method, the first circuit formation area includes an area constituted of dynamic memory cells, and the second circuit formation area includes an area in which peripheral circuits for driving the memory cells are formed.
According to a fourteenth aspect of the present invention, the method comprises the steps of:
(a) preparing a semiconductor substrate having an alignment mark area and an element formation area, the semiconductor substrate including an SOI substrate consisting of an underlying substrate, a buried insulating film formed on the underlying substrate and an SOI layer formed on the buried insulating film;
(b) forming first and second trenches at one time on the alignment mark area and the element formation area, respectively, so as to penetrate the SOI layer;
(c) forming an insulating film entirely on the surface of the SOI layer including the first and second trenches;
(d) removing the insulating film, the step (d) being performed so as to leave the insulating film which is buried in the second trench and remove all the insulting film on the center portion of the first trench while leaving the insulating film on the peripheral portion of the first trench as the alignment insulating film and further remove a part of the buried insulating film beneath the center portion of the first trench, the part of the semiconductor substrate which is removed being defined as the deepest portion of the first trench;
(e) forming an electrode layer entirely on the semiconductor substrate; and
(f) recognizing a position of the alignment mark and patterning the electrode layer on the element formation area. In the method of the fourteenth aspect, the alignment mark has a height difference between the highest portion of the alignment insulating film and a bottom surface of the deepest portion of the first trench.
According to a fifteenth aspect of the present invention, in the method, the second trench includes first and second circuit trenches being relatively narrow, the second circuit trench including a plurality of second circuit trenches, the plurality of second circuit trenches being formed so as to sandwich the SOI layer, the SOI layer sandwiched between the plurality of second circuit trenches being defined as a dummy layer, and the element formation area includes a first circuit formation area isolated by the first circuit trench and a second circuit formation area isolated by the plurality of second circuit trenches and the dummy layer.
According to a sixteenth aspect of the present invention, in the method, the electrode layer patterned in the step (f) is formed on the element formation area and includes a control electrode for controlling a device operation, and the method further comprises the steps of:
(g) entirely forming an interlayer insulating film;
(h) forming first and second through holes on the interlayer insulating film formed on the center portion of the first trench and the control electrode, respectively, the first through hole being formed so as to further penetrate the buried insulating film to reach the underlying substrate,
(i) forming a metal layer on the interlayer insulating film including the first and second through holes; and
(l) patterning the metal layer to form an interconnection layer.
According to a seventeenth aspect of the present invention, in the method, the semiconductor substrate further includes a circuit-on-underlying-substrate area, the step (b) includes the step of forming a third trench penetrating the SOI layer and being wider than each of the first and second trenches, and the step (d) includes the step of removing all the insulating film on the third trench and the buried insulating film beneath the third trench to expose the underlying substrate.
According to an eighteenth aspect of the present invention, in the method, the first circuit formation area includes an area constituted of dynamic memory cells, and the second circuit formation area includes an area in which peripheral circuits for driving the memory cells are formed.
In the semiconductor device of the first aspect of the present invention, the alignment insulating film has a height difference with the highest portion of the alignment insulating film being higher than the surface of the semiconductor substrate and the surface of the lowest portion being lower than the surface of the semiconductor substrate.
Therefore, even when an upper formation layer is formed on the semiconductor substrate including the alignment insulating film, the upper formation layer has another height difference reflecting the height difference of the alignment insulating film. It becomes easier to perform positional detection of the alignment mark with the height difference in the upper formation layer and a semiconductor device which is manufactured with high accuracy in positioning can be provided.
In the semiconductor device of the second aspect of the present invention, the alignment insulating film has a height difference between the highest portion and the bottom surface of the center portion of the first trench.
Therefore, even when the upper formation layer is formed on the semiconductor substrate including the alignment insulating film and the first trench, the upper formation layer has another height difference reflecting the height difference of the alignment insulating film. It becomes easier to perform positional detection of the alignment mark with the height difference in the upper formation layer and a semiconductor device which is manufactured with high accuracy in positioning can be provided.
In the semiconductor device of the third aspect of the present invention, since the first trench penetrates the SOI layer in the SOI substrate, a semiconductor device which is manufactured with high accuracy in positioning, like the semiconductor device of the second aspect, can be provided.
The semiconductor device of the fourth aspect of the present invention comprises the interlayer insulating film, the first through hole penetrating the deepest portion of the first trench and the interlayer insulating film to reach the underlying substrate, the second through hole penetrating the interlayer insulating film to reach the control electrode and the interconnection layer electrically connected to the control electrode through the second through hole.
When the interconnection layer is formed by etching after formation of the metal layer on the whole surface of the interlayer insulating film, the interconnection can be obtained with no etching damage since the underlying substrate and the control electrode are electrically connected to each other through the first and second through holes to reduce the potential difference therebetween, and a semiconductor device with excellent operation performance can be provided.
Moreover, since the deepest portion of the first trench is formed by removing a part of the buried insulating film, formation of the first through hole penetrating the buried insulating film beneath the deepest portion becomes relatively easy.
Since the semiconductor device of the fifth aspect of the present invention further comprises the element-on-underlying-substrate formation area being the underlying substrate in which semiconductor elements are formed, a semiconductor device in which semiconductor elements are formed in the underlying substrate as well as the SOI layer of the SOI substrate can be provided.
In the method for the semiconductor device of the sixth aspect of the present invention, by forming the resist pattern at least on the insulating film corresponding to the peripheral vicinity region external to the first trench in the alignment mark area in the step (d), removing the insulating film with the resist pattern used as a mask in the step (e) and further entirely removing the insulating film after removing the resist pattern in the step (f), the alignment mark has a height difference between the center portion and the peripheral portion in the first trench.
Therefore, since the electrode layer formed on the alignment mark has another height difference reflecting the height difference of the alignment mark, positional detection of the alignment mark in the step (h) becomes easy with the height difference in the electrode layer and patterning of the electrode layer is achieved on the basis of the alignment mark with high accuracy.
Since the resist pattern used in the step (e) is formed at least on the insulating film corresponding to the peripheral vicinity region external to the first trench in the alignment mark area, it is possible to prevent deterioration in detection accuracy of the alignment mark due to rounding of a fringe portion of the first trench as the result of removing the semiconductor substrate in the peripheral vicinity region of the first trench together with the insulating film after the step (f).
In the method for the semiconductor device of the seventh aspect of the present invention, the resist pattern used in the step (e) is further formed on the insulating film corresponding to the first trench in the alignment mark area, and the alignment mark includes the alignment insulating film which is the insulating film formed in the first trench, the alignment insulating film being formed so that the highest portion of the alignment insulating film formed on the peripheral portion is higher than the surface of the semiconductor substrate and the alignment insulating film formed on the center portion is lower than the surface of the semiconductor substrate to have a height difference.
Therefore, since the electrode layer formed on the alignment insulating film has another height difference reflecting the height difference of the alignment mark, the height difference of the electrode layer itself can be used as the alignment mark.
In the method for the semiconductor device of the eighth aspect of the present invention, the resist pattern is formed only on the insulating film corresponding to the peripheral vicinity region of the first trench in the alignment mark area, and the alignment mark includes the alignment insulating film and the first trench and has the height difference between its highest portion and the bottom surface of the deepest portion of the first trench.
Therefore, since the electrode layer formed on the alignment insulating film and the first trench has another height difference reflecting the height difference of the alignment mark, the height difference of the electrode layer itself can be used as the alignment mark.
In the method for the semiconductor device of the ninth aspect of the present invention, since the first trench formed in the step (b) penetrates the SOI layer in the SOI substrate, the semiconductor device can be manufactured with high accuracy in positioning on the SOI substrate.
In the method for the semiconductor device of the tenth aspect of the present invention, the interlayer insulating film is formed in the step (i), the first through hole penetrating the center portion of the first trench and the buried insulating film to reach the underlying substrate and the second through hole penetrating the interlayer insulating film to reach the control electrode are formed in the step (j) and the metal layer is formed on the interlayer insulating film including the first and second through holes in the step (k).
Therefore, in the patterning of the metal layer of the step (l), the interconnection layer can be obtained with no etching damage since the underlying substrate and the control electrode are electrically connected to each other through the first and second through holes to reduce the potential difference therebetween, and as a result a semiconductor device with excellent operation performance can be provided.
Moreover, since the deepest portion in the center portion of the first trench is formed by removing a part of the buried insulating film, formation of the first through hole penetrating the buried insulating film beneath the deepest portion becomes relatively easy.
In the method for the semiconductor device of the eleventh aspect of the present invention, since the underlying substrate is exposed in the step (f), the semiconductor elements can be formed in the underlying substrate as well as in the SOI layer of the SOI substrate by already-existing method in the later steps.
In the method for the semiconductor device of the twelfth aspect of the present invention, the element formation area includes the first circuit formation area isolated by the first circuit trench which is relatively narrow and the second circuit formation area isolated by the second circuit trench which is relatively wide.
Because of the nature that the insulating film formed on the first circuit trench which is narrow becomes thicker than that formed on the second circuit trench which is wide, it is necessary to remove the insulating film on the first circuit formation area more than that on the second circuit formation area and the step of selectively removing the insulating film on the first circuit formation area is needed.
For this reason, the resist pattern is formed on the second circuit formation area, not on the first circuit formation area in the step (d), to remove the insulating film on the first circuit formation area at one time.
In the method for the semiconductor device of the thirteenth aspect of the present invention, since the first circuit formation area of the semiconductor device manufactured by the method includes the area constituted of dynamic memory cells, it is possible to pattern the electrode layer in the dynamic memory cell with high accuracy.
In the method for the semiconductor device of the fourteenth aspect of the present invention, the insulating film is entirely removed, and the insulating film on the center portion of the first trench is all removed while that on the peripheral portion of the first trench is left as the alignment insulating film, and a part of the buried insulating film beneath the center portion of the first trench is also removed in the step (d), to obtain the height difference between the highest portion of the alignment insulating film and the bottom surface of the deepest portion of the first trench.
Therefore, since the electrode layer formed on the alignment insulating film and the first trench has another height difference reflecting the above height difference, positional detection of the alignment mark in the step (f) becomes easy with the height difference in the electrode layer and patterning of the electrode layer is achieved on the basis of the alignment mark with high accuracy.
Omitting the step of selectively removing the insulating film prior to the step (d) can simplify the manufacturing process.
In the method for the semiconductor device of the fifteenth aspect of the present invention, the element formation area includes the first circuit formation area isolated by the first circuit trench and the second circuit formation area isolated by the second circuit trench.
Since the second circuit formation area is isolated by the isolation area consisting of the plurality of second circuit trenches and the dummy layer, a wide isolation area is obtained by providing a wide dummy layer even if the second circuit trench is narrow itself.
Therefore, as the insulating films on the first circuit formation area and the second circuit formation area have the same thickness, no step of selectively removing the insulating film prior to the step (d) is needed.
In the method for the semiconductor device of the sixteenth aspect of the present invention, the interlayer insulating film is formed in the step (g), the first through hole penetrating the center portion of the first trench and the buried insulating film to reach the underlying substrate and the second through hole penetrating the interlayer insulating film to reach the control electrode are formed in the step (h) and the metal layer is formed on the interlayer insulating film including the first and second through holes in the step (i).
Therefore, in the patterning of the metal layer of the step (j), the interconnection layer can be obtained with no etching damage since the underlying substrate and the control electrode are electrically connected to each other through the first and second through holes to reduce the potential difference therebetween, and as a result a semiconductor device with excellent operation performance can be provided.
Moreover, since the deepest portion in the center portion of the first trench is formed by removing a part of the buried insulating film, formation of the first through hole penetrating the buried insulating film beneath the deepest portion becomes relatively easy.
In the method for the semiconductor device of the seventeenth aspect of the present invention, since the underlying substrate is exposed in the step (d) and the electrode layer is formed on the circuit-on-underlying-substrate area in the step (f), a semiconductor device in which the semiconductor elements can be formed on the SOI layer and the underlying substrate can be manufactured.
In the method for the semiconductor device of the eighteenth aspect of the present invention, since the first circuit formation area of the semiconductor device manufactured by the method includes the area constituted of dynamic memory cells, it is possible to pattern the electrode layer in the dynamic memory cell with high accuracy.
An object of the present invention is to provide a semiconductor device with trench isolation structure which allows an alignment with high accuracy, without deterioration of device performance, and a method for manufacturing the semiconductor device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.